I. Field of the Disclosure
The technology of the disclosure relates to static random access memory (SRAM) bitcells and resetting of SRAM bitcells.
II. Background
A memory cell is a basic building block of computer data storage, also known as “memory.” A computer system may either read data from or write data to memory. There are different types of memory. For example, one type of memory is static random access memory (SRAM). As an example, SRAM may be used as cache memory in a central processing unit (CPU) system. A SRAM cache memory may be comprised of a tag array and a data array. The tag array receives a memory address as part of a memory access request from a CPU. A portion of the memory address is stored as a tag in the tag array and a remaining portion of the memory address is used to index a location. Each tag entry has one or more corresponding entries in the data array. The entries in the tag array can be valid or invalid.
A tag will be valid if the data stored in the data entry in the data array of the SRAM cache memory corresponding to the tag is valid. In the case of a valid tag, the data for the memory access request can be directly accessed from the data array in the SRAM cache memory as opposed to being accessed from a higher level memory. If a tag accessed as part of a memory access request is invalid, the data stored in the data entry of the data array of the SRAM cache memory corresponding to the tag is deemed invalid. For example, the data in the data array corresponding to the invalid tag may not be updated to be coherent with the data stored at the memory address of the memory access request in higher memory. To indicate whether a tag in a SRAM cache memory is valid or invalid, a valid bit can be provided in the SRAM cache memory. The valid bit can be comprised of a single SRAM bitcell. A plurality of valid bits can be provided over a column of the SRAM cache memory, with each valid bit corresponding to a row in the SRAM cache memory. The value or state of a valid bit can be set to a logical high (“1”) to indicate that the tag is valid, and to a logical low (“0”) to indicate the tag is invalid, or vice versa. A cache miss is generated by the SRAM cache memory when the valid bit corresponding to the memory address of the memory access request is invalid in the tag array to prevent invalid data in the data array from being used to fulfill the memory access request.
During operation of a device containing SRAM cache memory, the valid bits in the SRAM cache memory will power up in a random, unknown state (i.e., an unknown charge level) of either logical one (“1”) or logical zero (“0”). Since the valid bits will power up in a random, unknown state, it may be desired to perform an invalidate operation to set or reset all of the valid bits in the tag array of the SRAM cache memory to an invalid state. In this manner, if the SRAM cache memory is accessed before being filled with valid data, the valid bits being set to an invalid state will cause a cache miss to occur.
One method of invalidating valid bits of SRAM cache memory involves individually resetting the state of each valid bit to an invalid state. However, this method of individually resetting the validity state of each of the valid bits is time consuming. Another method of resetting the valid state of an entire column of valid bits in an SRAM cache memory in a single reset operation involves providing the valid bits as specialized SRAM bitcells. The specialized SRAM bitcells include one or more additional transistors. Each of the additional transistors in the specialized SRAM bitcells is coupled to a voltage rail node and/or a ground rail node. Thus, an entire column of the specialized SRAM bitcells may be reset in a single reset operation by activating all of the additional transistors for each of the specialized SRAM bitcells to be coupled to the voltage rail node and/or the ground rail node to force the values of the specialized SRAM bitcells to an invalid state. However, providing the additional transistors for the valid bits increases the SRAM cache memory density. Specialized SRAM bitcells with additional transistors for an invalidate operation require a more complicated manufacturing process because of the smaller SRAM geometries.
One way to avoid the need to provide specialized SRAM bitcells while maintaining the ability to provide a single reset operation for valid bits in a SRAM cache memory is to provide a reset circuit having increased drive strength. The reset circuit may be the validity bitline driver that drives a bitline to a plurality of SRAM bitcells, such as a column of SRAM bitcells. The increased drive strength provides the additional current capacity for the validity bitline driver to be capable of forcing the load of an entire column of the valid bits in the SRAM cache memory to an invalid state in a single reset operation. However, providing additional drive strength in a validity bitline driver may increase the size of the validity bitline driver in the SRAM cache memory, thus increasing the size of the memory.
It is desired to provide for the capability of a single reset operation to reset a plurality of valid bits in the SRAM cache memory without the need to provide specialized SRAM bitcells or an increased drive strength validity bitline driver, each of which increase SRAM cache memory density.